1. Field of the Invention
The invention relates to a semiconductor device,, a process for manufacturing such a device, and more particularly, to a process for forming gate spacers.
2. Description of Related Art
In the fabrication of MOS devices on a substrate, the self-aligned silicide (SALICIDE) process is performed to decrease the sheet resistance of the MOS electrodes and the contact resistance of the contact regions between those electrodes.
For decreasing the above mentioned resistances well enough, the salicide process is performed at a high temperature. However, the salicide process cannot be performed as well as required at a temperature of more than about 750.degree. C., especially when the MOS devices comprises a P-type metal oxide semiconductor (PMOS). This is because at such a high temperature, the silicon material in the PMOS gate often oozes out to the spacer adjacent to the gate, and thereby transforms into salicide layers upon the spacer by reacting with the metal layer deposited on the spacer. The salicide layers upon the spacer undesirably, electrically connect the gate with the source/drain regions of the PMOS and often make the PMOS short during operation.
On the other hand, by lowering the temperature to less than about 750.degree. C., it is not easy for other devices, such as an N-type metal oxide semiconductor (NMOS), to form salicide layers upon them, especially when their gate widths are narrowed as the integration of the devices is increased. In addition, the above mentioned resistances cannot be decreased well enough by performing the salicide process at the above temperatures.